Digital PLL devices are widely used in digital telecommunication, and are present in various types. One of them is a digital PLL device having a phase switching and frequency dividers, which is introduced in "How to Use PLL-IC", by Masayasu Hata, Keisuke Furukawa, Feb. 10, 1986, Akiba Shuppan, page 139.
FIG. 2 is block diagram showing an example of this type of conventional digital PLL device. In FIG. 2, 1 is an input terminal, 2 is a phase comparator, 3 is a low-pass filter such as a random walk filter, 4 is a control circuit, 5 is an oscillator, 6 is a tapped delay circuit, 7 is a selection circuit, 8 is a delay circuit, 9 is a frequency divider, and 10 is an output terminal.
Digital signals applied to the input terminal 1 are input to the phase comparator 2, and its phase is compared with the phase of the output signal of the frequency divider 9. The comparison output of the phase comparator 2 is passed through the low-pass filter 3 where high-frequency components are removed, and is applied to the control circuit 4. The output signal of the oscillator 5 is input to the tapped delay circuit 6, which delays the output signal of the oscillator 5 within the range of 360.degree., and the signals having successively larger phase delays are output from the plurality of intermediate taps. For instance, eight signals are produced and the difference in phase delay between the successive signals is 45.degree.. The taps of the tapped delay circuit 6 are connected to the selection circuit 7. In accordance with the command from the control circuit 4, the selection circuit 7 selects one of the taps and connect the selected tap to its output, and the output signal from the selected tap is supplied to the frequency divider 9. That is, when the phase of the digital signal applied to the input terminal 1 is leading relative to the signal output from the output terminal 10, i.e., the output signal of the frequency divider 9, to advance the phase of the output signal of the frequency divider 9, the selection circuit 7 is switched to a tap producing a signal having a smaller phase delay than the signal that is currently selected. Accordingly, a signal having a phase leading the currently selected signal is supplied from the selection circuit 7 to the frequency divider 9. If it is still necessary to further advance the phase even when the tap having the smallest delay has been reached, then the tap having the largest delay is selected. The number n of the taps is related to the phase difference .theta. between adjacent taps as follows: EQU n=360.degree./.theta.
Switching to the tap having the largest delay (having the phase n.theta.) will result: EQU .theta.-(n.theta.)=.theta.-360.degree.=.theta.
Thus, the difference in angle is again .theta., and the continuity of the phase variation is maintained. In this way, the phase of the signal to the frequency divider 9 is advanced a predetermined angle at a time until the phase of the input digital signal and the phase of the output signal of the frequency divider 9 coincide with each other. The operation for retarding the phase is similar.
During switching of the phase, the signal currently selected and the signal to be selected next have different digital values of "1" and "0", hazard occurs in the output signal because of the phase switching, and the operation of the frequency divider 9 is interfered. For instance, in FIG. 3, (A), (B), (D) and (F) are waveforms being concurrently output from the taps of the tapped delay circuit 6. (A) and (D) are waveforms of the signal currently selected before the phase switching (hereinafter referred to as waveforms before switching). (B) and (E) are waveforms of the signals which are to be selected after the phase switching (hereinafter referred to as waveforms after switching). (C) and (F) are waveforms of the output of the selection circuit 7. T1 and T2 denote the timing at which the switches of the selection circuit are operated. In the case of FIG. 3, the waveform before switching (A) and the waveform of after switching (B) have different digital values "1" and "0", and the output waveforms is associated with a hazard before and after the timing T1, as shown by (C). Accordingly, if the frequency divider 9 performs the frequency-division by counting the leading edges of the input waveform, an erroneous frequency-division will occur due to the hazard. If the switching takes place at timing T2 when the waveforms before switching (D) and the waveforms after switching (E) have identical digital values "1" and "0", no hazard will occur. The delay circuit 8 shown in FIG. 2 is provided for determining this timing. For instance, if the difference between the successive taps of the tapped delay circuit 6 is 45.degree. , the waveforms after the switching is either 45.degree. leading or 45.degree. lagging, as shown in FIG. 4 at (H) and (I), relative to the waveform before switching shown at (H). Accordingly, if the switching is effected at a timing 90.degree. lagging behind the leading edge of the waveform before the switching, the hazard can be avoided. In this case, the delay circuit 8 is set to have a phase delay of 90.degree. of the input signal. The delay circuit 8 is normally in the digital type.
With the above-described digital PLL device, when the operating frequency is increased and high-speed operation is required, the operation delay time at each part imposes a limitation. For instance, due to the delay time of the selection circuit 7, the control circuit 4 and the delay circuit 8 shown in FIG. 2 (this overall delay time will hereinafter referred to as loop delay time), the phase switching timing T.sub.3 lags as shown in FIG. 4. In the example shown in FIG. 4, when the loop delay time exceeds the time corresponding to 45.degree., hazard as shown at (C) in FIG. 3, and the frequency divider 9 operates erroneously, and the overall operation becomes inappropriate. The maximum operation frequency of the digital PLL device is therefore limited by the loop delay time corresponding to 45.degree..